100 Days of RTL

Introduction

Completing the #100DaysOfRTL challenge changed me a lot. When I started, my main goal was to better understand RTL design by practicing regularly. I didn't realize how much it would improve my skills, mindset, and career perspective.

RTL design isn’t just about coding in Verilog it’s about thinking in hardware. Once I understood this, my entire perspective on digital electronics changed. However, I struggled with maintaining consistency. While I understood the theory, applying it to create functional code and verified designs required discipline. This challenge pushed me to code daily, document my progress, and develop habits that would prepare me for the industry.

Throughout the 100 days,

Day	Task	link
Day 1	AND Gate using Verilog HDL.	Click me for code capsule
Day 2	OR Gate.	Click me for code capsule
Day 3	NOT Gate.	Click me for code capsule
Day 4	NAND Gate.	Click me for code capsule
Day 5	NOR Gate.	Click me for code capsule
Day 6	XOR Gate.	Click me for code capsule
Day 7	XNOR Gate.	Click me for code capsule
Day 8	Half Adder.	Click me for code capsule
Day 9	Full Adder.	Click me for code capsule
Day 10	4-bit Full Adder using Verilog.	Click me for code capsule
Day 11	Ripple Carry Adder (4-bit).	Click me for code capsule
Day 12	2:1 Multiplexer.	Click me for code capsule
Day 13	Half Subtractor using Verilog HDL.	Click me for code capsule
Day 14	Full Subtractor in Verilog HDL.	Click me for code capsule
Day 15	4-bit Adder/Subtractor in Verilog HDL.	Click me for code capsule
Day 16	Carry Lookahead Adder (CLA) in Verilog HDL.	Click me for code capsule
Day 17	4:1 Multiplexer using Verilog HDL.	Click me for code capsule
Day 18	Inverter using a 2:1 MUX.	Click me for code capsule
Day 19	5:1 Multiplexer using only 2:1 MUXes.	Click me for code capsule
Day 20	8:1 Multiplexer.	Click me for code capsule
Day 21	Full Subtractor using 8x1 MUX.	Click me for code capsule
Day 22	Full Subtractor using 4x1 Multiplexers in Verilog HDL.	Click me for code capsule
Day 23	Full Subtractor using only 2:1 Multiplexers.	Click me for code capsule
Day 24	3-bit Gray to Binary Converter using 4:1 MUXes.	Click me for code capsule
Day 25	10x1 Multiplexer using 4x1 Multiplexers.	Click me for code capsule
Day 26	1:2 Demultiplexer (DEMUX).	Click me for code capsule
Day 27	1:4 Demux in Verilog today.	Click me for code capsule
Day 28	Full Adder using 1:4 Demux.	Click me for code capsule
Day 29	1:2 Demux using a 1:4 Demux.	Click me for code capsule
Day 30	4:1 MUX using 2:1 MUXes.	Click me for code capsule
Day 31	1:4 DeMUX using 1:2 DeMUX.	Click me for code capsule
Day 32	Encoder vs Priority Encoder – Quick Difference.	Click me for code capsule
Day 33	8:3 Encoder vs 8:3 Priority Encoder.	Click me for code capsule
Day 34	3:8 Decoder using 2:4 Decoders.	Click me for code capsule
Day 35	Gray to Binary Converter using 3:8 Decoder.	Click me for code capsule
Day 36	N-bit Full Adder using Parameter Overriding.	Click me for code capsule
Day 37	2-to-4 Decoder using 4:1 MUX.	Click me for code capsule
Day 38	4-to-2 Encoder using 2:1 MUX.	Click me for code capsule
Day 39	1-bit comparator in Verilog HDL.	Click me for code capsule
Day 40	2-bit comparator in Verilog by instantiating and connecting multiple 1-bit comparator modules from the previous design.	Click me for code capsule
Day 41	N-bit comparator in Verilog using parameterized.	Click me for code capsule
Day 42	Binary-to-Gray Code Converter in Verilog HDL.	Click me for code capsule
Day 43	Gray-to-Binary code conversion in Verilog HDL.	Click me for code capsule
Day 44	N-bit Full Adder	Click me for code capsule
Day 45	7:1 Multiplexer using 2:1 Multiplexers	Click me for code capsule
Day 46	Designed a 3-bit Operation ALU using Verilog HDL.	Click me for code capsule
Day 47	A deep dive into Verilog event scheduling and specifically what happens at the c (Non-Blocking Assignment region).	Click me for code capsule
Day 48	Simple 8x8 Synchronous RAM in Verilog HDL.	Click me for code capsule
Day 49	Prime number checking in Verilog.	Click me for code capsule
Day 50	Factorial module in Verilog HDL using a recursive function.	Click me for code capsule
Day 51	NOR latch (SR latch using cross-coupled NOR gates) in Verilog HDL.	Click me for code capsule
Day 52	Odd Parity Generator in Verilog HDL.	Click me for code capsule
Day 53	Verilog testbench to count the number of 1’s in a 32-bit vector using a parameterized function.	Click me for code capsule
Day 54	SR Latch using NAND Gates.	Click me for code capsule
Day 55	SR Latch using 4 NAND gates.	Click me for code capsule
Day 56	Examples of Compiler Directives.	Click me for code capsule
Day 57	Half Adder using a 2-to-4 Decoder.	Click me for code capsule
Day 58	Clock Generation (tp=10ns (100MHZ)-- and tp=5ns(200MHZ)).	Click me for code capsule
Day 59	Duty cycle generation using Verilog.	Click me for code capsule
Day 60	Understanding Jitter with Real Examples.	Click me for code capsule
Day 61	SR Latch with Enable using NAND gates.	Click me for code capsule
Day 62	D latch level-sensitive.	Click me for code capsule
Day 63	Positive level D latch using a 2:1 multiplexer.	Click me for code capsule
Day 64	Negative level-sensitive D latch using a 2:1 multiplexer.	Click me for code capsule
Day 65	A Positive Edge-Triggered D Flip-Flop using two D latches in master–slave.	Click me for code capsule
Day 66	D Flip-Flop Negative edge in Verilog using the master–slave latch design.	Click me for code capsule
Day 67	D Flip-Flop in Verilog HDL.	Click me for code capsule
Day 68	SR Flip-Flop in Verilog HDL.	Click me for code capsule
Day 69	T Flip-Flop in Verilog HDL.	Click me for code capsule
Day 70	JK Flip-Flop in Verilog HDL.	Click me for code capsule
Day 71	JK Flip-Flop using an SR Flip-Flop.	Click me for code capsule
Day 72	D Flip-Flop using an SR Flip-Flop.	Click me for code capsule
Day 73	T Flip-Flop using an SR Flip-Flop.	Click me for code capsule
Day 74	SR Flip-Flop using a D Flip-Flop.	Click me for code capsule
Day 75	JK Flip-Flop using a D Flip-Flop using 2*1 mux.	Click me for code capsule
Day 76	T Flip-Flop using a D Flip-Flop.	Click me for code capsule
Day 77	SR Flip-Flop using a JK Flip-Flop.	Click me for code capsule
Day 78	D Flip-Flop using a JK Flip-Flop.	Click me for code capsule
Day 79	T Flip-Flop using a JK Flip-Flop.	Click me for code capsule
Day 80	SR Flip-Flop using a T Flip-Flop..	Click me for code capsule
Day 81	D Flip-Flop using a T Flip-Flop.	Click me for code capsule
Day 82	JK Flip-Flop using a T Flip-Flop.	Click me for code capsule
Day 83	3-bit asynchronous ripple counter using T flip-flops.	Click me for code capsule
Day 84	3-bit Up Counter using JK Flip-Flops.	Click me for code capsule
Day 85	3-bit Down Counter using JK Flip-Flops.	Click me for code capsule
Day 86	3-bit sequence counter using T flip-flops (0 → 1 → 2 → 3 → 4 → 5 → 7 → 0 →)	Click me for code capsule
Day 87	mod5 synchronous counter using behavioral modeling.	Click me for code capsule
Day 88	3-bit synchronous counter	Click me for code capsule
Day 89	decade counter.	Click me for code capsule
Day 90	4-bit ring counter using behavioral modeling.	Click me for code capsule
Day 91	4-bit Parallel In Parallel Out (PIPO) register	Click me for code capsule
Day 92	4-bit Serial In Parallel Out (SIPO) register	Click me for code capsule
Day 93	4-bit Serial In Serial Out (SISO) register	Click me for code capsule
Day 94	Melay Sequence Detector (Non-Overlapping)	Click me for code capsule
Day 95	Melay Sequence Detector 1101 (Overlapping)	Click me for code capsule
Day 96	Moore Sequence Detector (Overlapping)101.	Click me for code capsule
Day 97	Moore Sequence Detector (Non-Overlapping)101.	Click me for code capsule
Day 98	Mealy Sequence Detector to detect the pattern 1110.	Click me for code capsule
Day 99	Memory Project	Click me for code capsule
Day 100	FIFO: Synchronous & Asynchronous	Click me for code capsule

Some days were smooth, while others involved hours of debugging. These challenges taught me invaluable lessons.

Key Learnings:

Consistency Over Motivation: Discipline was more crucial than motivation. Consistent effort, even for short periods, built momentum.
Thinking in Hardware: My perspective shifted from coding to understanding hardware behavior, which is vital for an RTL engineer.
Debugging as a Skill: I embraced errors as learning opportunities. Debugging became a crucial part of understanding my designs.
Sharing Builds Confidence: Documenting my progress helped simplify concepts, benefiting both myself and others.
Building a Portfolio: I now have a comprehensive portfolio of modules, designs, and verification approaches to showcase.

Why #100DaysOfRTL Matters:

For students and freshers in RTL/VLSI, this challenge offers hands-on practice beyond textbooks, demonstrates commitment to recruiters, helps build a visible portfolio, and shifts learning from passive theory to active design and verification.

Completing #100DaysOfRTL was about more than just writing Verilog or debugging waveforms. It was about developing habits, thinking like an engineer, and pushing myself to grow. If you're considering a similar journey, whether in RTL, coding, or any other skill, I highly recommend it. The transformation is gradual, but after 100 days, you'll see significant growth.

Key Concepts and Components:

Combinational Circuits: Generate outputs based solely on current inputs, performing logical operations with components like adders and multiplexers.
Sequential Circuits: Have memory elements, with outputs depending on current inputs and past states, using components like flip-flops and counters.

Both are essential for designing complex digital systems.

Resources and Tools Used:

ModelSim: For simulating and checking HDL designs.
Quartus Prime: For developing FPGA and CPLD, providing a complete environment for RTL design.
Canva: Used for creating presentations, Posters and documents to showcase projects.

These tools were instrumental in designing, simulating, and presenting my RTL projects effectively.

Today marks the completion of my 100 days of RTL journey a path filled with challenges, learning, and growth.

I’m truly grateful for this experience and for the consistency it helped me build. A special thanks to

Chinna Venkata Narayana Reddy Seelam, who inspired me to start and stay consistent throughout this journey.